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Verilog Implemetation of AES Co Processor
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Posted By:
john basha
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The widespread increase in networking has led to a large number of networks resulting in continuous data flow that requires the encryption operation (for these data) to run continuously on the processor taking a major share of the processor time affecting its overall performance. Due to the other overheads running on the processor the encryption data rate also suffers and becomes dependent on the number of overheads.
Hence the logical solution is to replace the encryption overhead on the main processor by a dedicated hardwired cryptographic coprocessor(FPGA) working in tandem with the main processor according to the AES as proposed by NIST, for its high security and increased computational efficiency. The coprocessor we have designed in Verilog has a functionally pipelined architecture; it shares the data bus of the main processor and works by means of control signals and handshaking signals from the main processor.
The advantage of this crypto coprocessor is that it can be coupled with any processor and hence be easily incorporated into any application.
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