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JFET circuit designing in SPICE

Posted Date: Total Responses: 0 Posted By: Puneet Verma Member Level: Gold Points/Cash: 4

Hello people,

This project is for engineering students studying in 2nd, 3rd year in electronics. Our main aim is to design a circuit of JFET as our data provided and then further use it in PSPICE. I wont tell you everything about PSPICE because this project is for an engineer of 3rd year and that knowledge i can expect you to have because you must have studies that subject. Also it will be a very detailed project then.

So lets get started.

First go through the data as provided to you in the project or question.

Calculate all the paramenters which you need to have for modelling.I will tell you later what parameters you need.
The JFET model consists of parameters which are necessary to represent the device characteristics.

Rs and Rd resistance value would be given to you. These appear in series with the source, drain terminals. Diodes are connected between the gate and internal source and drain terminals.

Calculate the following parameter by equation:

Triode region-->

id= 2.BETA(vgs-VTO-vds/2)vds(1+LAMBDA.vds)

for vds-VTO>=vds>=0
Transconductance parameter BETA is given as

BETA=Idss/(Vp)square

Now here are the parameters which you need to have or calculate

Ohmic source resistance
ohmic drain resistance
Gate diode saturation current
Zero bias gate drain capacitance
Zero bias gate source capacitance
Pinch off voltage
Zero bias drain current
Transconductance
Gate bulk capacitance per unit width

After you have these parameters go to pspice program

Now you just need to draw the circuit as in your problem:

Main part is how to represent these parameters in program:

Remember: Letters are case sensitive, so put the values as provided.
for
Ohmic source resistance

put the value as RS in psice and enter value as provided or calculated.

for
ohmic drain resistance
put the value as RD in psice and enter value as provided.

similarly for
Gate diode saturation current (Is) put it as IS default value is 10fA.

Zero bias gate drain capacitance (Cgd)
CGD and enter the value

Zero bias gate source capacitance (Cgs)
CGS

Pinch off voltage (Vp)
VTO

Zero bias drain current (Not needed)

Transconductance
BETA

Gate bulk capacitance per unit width (Cgbo)
CGBO

Thats it your done then.your model design is ready.

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